This introductory chapter provides the reader with general knowledge on general-purpose DSP processors and also provides an up to date TMS320Cxx roadmap to show the evolution of Texas Instruments DSP chips in terms of processing power.

The objective of this chapter is to provide a comprehensive description of the ‘C6x architecture. This a includes detailed description of the central processing unit (CPU) and program control along with an overview of the memory organisation, serial ports, boot function and internal timer.

This chapter is divided into three main parts: the first part describes the software development tools, the second part describes the Evaluation Module (EVM) and finally the third part describes the codec and the use of interrupts and shows some useful programs for testing the TMS320C6201 EVM.

To introduce the need for code optimisation, this Chapter starts by introducing the concept of pipelining. Since with the TMS320C62x and the TMS320C67x, there are up to eight units, which are dedicated for different operations to work in parallel and also since different instructions can have different latencies, the programmer or the tools are left with the burden of scheduling the code. Backed with examples, this chapter explains the different techniques to optimise DSP code on these processors. (No source codes.)

The main purpose of this chapter is twofold. First it is to show how to design an FIR filter and implement it on the TMS320C62xx processor and secondly to show how to optimise code using knowledge gained in Chapter 3. This chapter also shows how to interface C and assembly, how to use intrinsics and put into practice material which has been covered in the previous chapters.

This chapter introduces the IIR filters and describes the two popular design methods, that is the bilinear and the impulse invariant methods and the realisations methods. Step by step, this chapter shows the procedures necessary to implement typical IIR filters specified by their transfer functions. Finally this chapter provides complete implementation of an IIR filter in C language, assembly and linear assembly and also shows how to interface C and linear assembly.

This chapter starts by introducing the need for an adaptive filter in communications. It then shows how to calculate the filter coefficients using the MSE criterion, exposes the least mean square (LMS) algorithm and finally, shows how the LMS algorithm is implemented in both C and Assembly.

This chapter deals with DTMF detection and provides a practical example of the Goertzel algorithm. This Chapter also shows how to produce optimised code by the pen and paper method and linear assembly and demonstrates how to program the Direct Memory Access, DMA.

This chapter starts by introducing the need for video compression to reduce the channel bandwidth requirement, then explains the implementation of the Joint Photographic Experts Group (JEPG) image codec. This includes detailed discussion and implementation of the DCT and IDCT and concentrates on the DCT and IDCT optimisation. The PC- DSP communication is also provided.